Field of the Invention
The present invention is generally directed to computer systems. More particularly, the present invention is directed to an architecture for unifying the computational components within a computer system.
Background Art
The desire to use a graphics processing unit (GPU) for general computation has become much more pronounced recently due to the GPU's exemplary performance per unit power and/or cost. The computational capabilities for GPUs, generally, have grown at a rate exceeding that of the corresponding central processing unit (CPU) platforms. This growth, coupled with the explosion of the mobile computing market (e.g., notebooks, mobile smart phones, tablets, etc.) and its necessary supporting server/enterprise systems, has been used to provide a specified quality of desired user experience. Consequently, the combined use of CPUs and GPUs for executing workloads with data parallel content is becoming a volume technology.
However, GPUs have traditionally operated in a constrained programming environment, available primarily for the acceleration of graphics. These constraints arose from the fact that GPUs did not have as rich a programming ecosystem as CPUs. Their use, therefore, has been mostly limited to 2D and 3D graphics and a few leading edge multimedia applications, which are already accustomed to dealing with graphics and video application programming interfaces(APIs).
With the advent of multi-vendor supported OpenCL™ and DirectCompute®, standard APIs and supporting tools, the limitations of the GPUs in traditional applications has been extended beyond traditional graphics. Although OpenCL and DirectCompute are a promising start, there are many hurdles remaining to creating an environment and ecosystem that allows the combination of a CPU and a GPU to be used as fluidly as the CPU for most programming tasks.
Existing computing systems often include multiple processing devices. For example, some computing systems include both a CPU and a GPU on separate chips (e.g., the CPU might be located on a motherboard and the GPU might be located on a graphics card) or in a single chip package. Both of these arrangements, however, still include significant challenges associated with (i) separate memory systems, (ii) efficient scheduling, (iii) providing quality of service (QoS) guarantees between processes, (iv) programming model, and (v) compiling to multiple target instruction set architectures (ISAs)—all while minimizing power consumption.
For example, the discrete chip arrangement forces system and software architects to utilize chip to chip interfaces for each processor to access memory. While these external interfaces (e.g., chip to chip) negatively affect memory latency and power consumption for cooperating heterogeneous processors, the separate memory systems (i.e., separate address spaces) and driver managed shared memory create overhead that becomes unacceptable for fine grain offload.
Although a CPU and a GPU traditionally performed different tasks, many types of workloads may be performed using a CPU or a GPU. When either CPU or GPU is free, the computing environment benefits if a workload can be redistributed between the processors.
Prior to processing, a workload is divided into many discrete tasks. Each task is assigned to a work queue associated with either a CPU or a GPU. Conventional computing environments, which include CPUs and GPUs, do not allow work redistribution to a processing device of a different type once a task is assigned to a CPU or a GPU for processing. Conventional systems allow CPUs to redistribute tasks to other CPUs, whereas the GPU does not have the functionality to redistribute work. This also hampers processing because CPUs may be busy while GPUs are free, and vice versa. The unbalanced processing results in inefficiencies and sub-optimal performance, particularly when a task can be processed on either processing device.